The present invention is directed to oscillator systems. More particularly, the invention provides a high-precision oscillator system with feed forward compensation. Merely by way of example, the invention has been applied to cold-cathode fluorescent lamp (CCFL) backlight driver systems. But it would be recognized that the invention has a much broader range of applicability. For example, the present invention can be applied to integrated circuit systems other than CCFL backlight driver systems. In another example, the present invention can be applied to devices other than integrated circuits.
An oscillator system is often used as an important component for pulse-width-modulation (PWM) control in a cold-cathode fluorescent lamp (CCFL) backlight driver system. For example, the oscillator system can generate a high-frequency clock signal for internal timing control and a high-frequency ramp signal that is compared to an error signal.
FIG. 1(A) and (B) are simplified diagrams showing a conventional PWM control system. The PWM control system 100 includes an error amplifier 110, an oscillator 120, a PWM comparator 130, a capacitor 140, and a driver 150. The oscillator 120 is configured to generate a ramp signal 122 and a clock signal 124. Additionally, the oscillator 120 is coupled to a resistor 192, which can be used to adjust the frequency of the ramp signal 122 and the clock signal 124.
The error amplifier 110 receives a reference voltage Vref at the “+” terminal and a feedback voltage VFB at the “−” terminal. The feedback voltage indicates the magnitude of the current that follows through a CCFL 160. The difference between the reference voltage and the feedback voltage is amplified by the error amplifier 110, whose output terminal 116 is connected to the capacitor 140. The capacitor 140 is used as the compensation network for system loop stability.
As shown in FIG. 1(A) and (B), the capacitor 140, together with the error amplifier 110, outputs a CMP signal 142 to the PWM comparator 130. The PWM comparator 130 also receives the ramp signal 122 from the oscillator 120. The ramp signal 122 is compared to the CMP signal 142 by the PWM comparator 130, which sends a PWM control signal 132 to the driver 150. The duty cycle of the PWM control signal 132 depends at least in part on the comparison between the CMP signal 142 and the ramp signal 122.
The driver 150 receives the PWM control signal 132 and outputs a PWM drive signal 152 to a power stage 165. From the power stage 165, the power is transferred to an output stage through a transformer 190. The current that flows through the CCFL 160 is converted into the feedback voltage by a resistor 195.
FIG. 2 is a simplified diagram showing conventional waveforms for the PWM control system 100 as shown in FIG. 1(A) and (B). The PWM comparator 130 receives the CMP signal 142 at the “+” terminal and the ramp signal 122 at the “−” terminal. If the voltage of the CMP signal 142 is higher than the voltage of the ramp signal 122, the voltage of the PWM signal 132 is at the logic high level. If the voltage of the CMP signal 142 is lower than the voltage of the ramp signal 122, the voltage of the PWM signal 132 is at the logic low level. Hence, the duty cycle of the PWM signal 132 is determined by the waveforms of the CMP signal 142 and the ramp signal 122. Additionally, the frequency of the PWM signal 132 is the same as the ramp signal 122 and the clock signal 124, both of which are generated by the oscillator 120. The frequency of the ramp signal 112 is independent of the input voltage VIN, and the upward slope of the ramp signal 112 is independent of the input voltage VIN.
FIG. 3 is a simplified diagram showing the conventional oscillator 120, and FIG. 4 is a simplified diagram showing conventional waveforms for the oscillator 120.
As shown in FIG. 3, the oscillator 120 includes voltage comparators 305 and 310, a capacitor 320, and switches 325 and 330. The voltage comparators 305 and 310 use internal reference voltages VH and VL as threshold voltages respectively. The reference voltage VH is set higher than the reference voltage VL.
For the capacitor 320, the current IC serves as the charging current, and the current ID serves as the discharging current. Specifically, after the oscillator 120 is activated, the switch 325 is closed and the switch 330 is open. The current IC then charges the capacitor 320, which outputs a voltage 322. The voltage 322 is the ramp signal 122. If the voltage 322 becomes higher than the reference voltage VH, the switch 325 is open and the switch 330 is closed. Consequently, the current IC stops charging the capacitor 320, and the current ID starts discharging the capacitor 320.
When the voltage 322 becomes lower than the reference voltage VL, the switch 325 is again closed and the switch 330 becomes again open. Then, the current ID stops discharging the capacitor 320, and the current IC starts charging the capacitor 320 until the voltage 322 becomes higher than the reference voltage VH again. As shown in FIG. 3, the capacitor 320 is internal to the chip where the oscillator 120 is located. The chip can also include a trimming circuit to improve the precision and consistency of the oscillation frequency. In another example, the currents IC and ID are determined by the resistor 192.
As shown in FIG. 4, this charging and discharging process for the capacitor 320 often continues. Additionally, each charging period is represented by TON, and each discharging period is represented by TOFF.
                              T          ON                =                                            (                                                V                  H                                -                                  V                  L                                            )                        ×                          C              O                                            I            C                                              (                  1          ⁢          A                )                                          T          OFF                =                                            (                                                V                  H                                -                                  V                  L                                            )                        ×                          C              O                                            I            D                                              (                  1          ⁢          B                )            
Where C0 represents the capacitance value of the capacitor 320. Hence,
                              f          s                =                              1                                          T                ON                            +                              T                OFF                                              =                                    1                                                (                                                            V                      H                                        -                                          V                      L                                                        )                                ×                                  C                  O                                                      ×                                                            I                  C                                ×                                  I                  D                                                                              I                  C                                +                                  I                  D                                                                                        (        2        )            
Where fs represents the frequency of the ramp signal 122 and the clock signal 124. Also, for example, the duty cycle D of the ramp signal 122 is
                    D        =                              T            ON                                              T              ON                        +                          T              OFF                                                          (        3        )            
The conventional PWM control system as described above often has one or more disadvantages. For example, if the input voltage VIN changes, the current flowing through the CCFL may change instantly, but the feedback loop has a relatively slow response. Hence the dynamic adjustment of the PWM control system is usually not sufficiently fast.
The conventional PWM control system can be improved by using a forward feed compensation technique. The forward feed compensation technique can, to certain extent, improve the dynamic response and reliability of the conventional PWM control system. Since the ramp signal is usually generated by an oscillator, the feed forward technique has been implemented in the conventional oscillator design.
FIG. 5 is a simplified diagram showing a conventional oscillator system with feed forward compensation, and FIG. 6 is a simplified diagram showing conventional timing relationship for the PWM control system using the oscillator system as shown in FIG. 5.
As shown in FIG. 5, a resistor 502 and a capacitor 504 are external to a control chip 510, and used to adjust the output frequency of the oscillator system. Additionally, resistors 522 and 524 are internal to the control chip 510 and used to determine a compensation ratio. The ramp signal 550 of the oscillator system is output at a node 506.
At the beginning, the voltage level of the ramp signal 550 increases as a result of charging the capacitor 504 by the input voltage VIN through the resistor 502. If the voltage level at the node 506 becomes higher than the reference voltage VH, a comparator 532 outputs a voltage 534 at the logic low level. Since the reference voltage VL is lower than the reference voltage VH, a comparator 536 in contrast outputs a voltage 538 at the logic high level. The output voltages 534 and 536 are processed by logic gates 540, 542, and 544. The logic gates 540 and 542 form a RS flip-flop, and the logic gate 544 is a NOT gate.
If the voltage 534 is at the logic low level and the voltage 538 is at the logic high level, the NOT gate 544 would output a voltage 546 at the logic high level. Consequently, a transistor 560 is turned on and the capacitor 504 is discharged. When the voltage level of the ramp signal at the node 506 becomes lower than the reference voltage VL, the voltage 546 is changed to the logic low level, which causes the transistor 560 to be turned off. Consequently, the input voltage VIN starts re-charging the capacitor 504.
As shown in FIGS. 5 and 6, the reference voltage VH changes with the input voltage VIN. Specifically,
                              V          H                =                                            R              1                                                      R                1                            +                              R                2                                              ⁢                      V            IN                                              (        4        )            
Where R1 and R2 represent resistance values of the resistors 522 and 524 respectively. Additionally, the reference voltage VL is often set to a very low level, such as 0.1 volt. As shown in FIG. 6, the ramp signal 550 increases from the reference voltage VL to the reference voltage VH, and then decreases from the reference voltage VH to the reference voltage VL.
As shown in FIG. 6, if the input voltage VIN increases, the reference voltage VH also increases. Consequently, the frequency of the ramp signal 550 is determined as follows:
                              f          r                =                  1                                    R              T                        ×                          C              T                        ×            ln            ⁢                                                  ⁢                                          V                IN                                                              V                  IN                                -                                  V                  H                                                                                        (        5        )            
where fr represents the frequency of the ramp signal 550, RT represents the resistance value of the resistor 502, and CT represents the resistance value of the capacitor 504. Additionally, as discussed above, FIG. 6 is a simplified diagram. In more detail, the upward slope of the ramp signal 550 increases with the input voltage VIN.
The conventional feed forward compensation technique often does not provide high precision and stability for the oscillation frequency. Hence it is highly desirable to improve the techniques for oscillation systems.